The present invention is directed, in general, to semiconductor manufacturing and, more specifically, to a method of manufacturing a channel stop implant in a semiconductor device and an integrated circuit incorporating the same.
The rapid evolution of integrated circuits imposes on the semiconductor industry the need for creating an efficient and reliable process to separate active devices that function on the present miniaturized scale. Semiconductor devices are being formed on the silicon substrates of integrated circuits at increasingly higher device densities and smaller feature sizes. The rapid process of device miniaturization, as well as the increased density of these devices, continues to present problems of semiconductor device design, manufacturing and operation.
Among the typical problems is the inadvertent formation of parasitics between the isolation regions of adjacent semiconductor devices. As devices such as metal oxide semiconductor (MOS) transistors are formed on a substrate, the isolation region, which is the region surrounding the active region of such a device, may inadvertently have an inversion layer formed therein. The formation of such an inversion layer may lead to parasitic current leakage between adjacent devices, especially in NMOS applications. Typically, an inversion layer may be formed in the isolation region of a device when the device is operated if the dopant dose of the isolation region is substantially equal to the dopant dose found in the active region.
To combat the formation of parasitics in the isolation region of adjacent devices, techniques have been developed to increase the threshold voltage of the material in the isolation region, typically up to ten times or more than that of the active region. Usually, the threshold voltage of the isolation region is designed to be in excess of the operating voltage of the device. In the case of a MOS transistor, perhaps the most common technique involves heavily doping the isolation region with boron, or other similar dopant, before field oxides are formed around the device. This approach forms a channel stop implant (xe2x80x9cchanstopxe2x80x9d) in the isolation region to help prevent parasitic leakage. In addition, as the threshold voltage in the isolation region increases, source-to-drain current leakage within the device itself is also reduced.
Unfortunately, implanting a chanstop using such a technique is not without problems. For example, as the substrate is oxidized to form the field oxides, much of the boron implanted to form the chanstop can be oxidized away. The thicker the field oxides grown, the more boron that is oxidized away. As a result, extremely high levels of dopant are typically needed in the anticipation of high loss during field oxide oxidation. In addition, conventional methods for implanting chanstops include blanket depositing the dopant over a large portion of the device. By blanket depositing the dopant in this manner, the high dopant dose is often diffused in areas of the device where it is not needed, rather than concentrated in the areas where it is needed. Those who are skilled in the art understand the problems that may arise from high levels of stray dopant in undesirable areas.
Furthermore, those skilled in the art understand that as the dopant dosage in the isolation region is increased, the breakdown voltage of the nearby active region is typically decreased. In some cases, the needed high doses can decrease the breakdown voltage by nearly one half its original value. Of course, device strength and longevity may be compromised as the breakdown voltage is decreased. As discussed above, however, if the doses are lowered in an attempt to maintain a high breakdown voltage and prevent device failure, the threshold voltage of the isolation region is decreased and the formation of inversion layers leading to parasitics is typically the result.
In the prior art, a common solution to this decrease in breakdown voltage is to simply xe2x80x9cpull backxe2x80x9d the chanstop implant away from the active region (e.g., source and drain regions). Unfortunately, pulling the chanstop implant away from the active region can lower the dopant concentration in the channel defined by the source and drain. As its dopant dosage decreases, the threshold voltage of the source-to-drain channel, thus, may also decrease. As a result, the likelihood of source-to-drain leakage increases.
As can be seen from the above discussion, as the dopant dosage in the chanstop implant are increased to prevent parasitic leakages between devices and to combat source-to-drain leakage within a device, the high doses near the active region decrease the breakdown voltage of the device. However, if the chanstop implant is pulled away from the active region to maintain the breakdown voltage, the lowered dopant concentration in the source-to-drain channel area increases the likelihood of source-to-drain leakage. Accordingly, what is needed in the art is a method of forming a channel stop implant that prevents parasitic leakages between devices and combats source-to-drain leakage, yet does not significantly decrease the breakdown voltage of the device.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes creating a source/drain region between an electrode and an isolation structure located in a substrate. In addition, the method includes implanting a dopant at a predetermined implant dopant concentration through an opening formed in a channel stop mask and located between the electrode and the isolation structure to form a channel stop between the source/drain region and the isolation structure.
In another aspect, the present invention provides a method of manufacturing an integrated circuit. In one embodiment, the method includes creating a source/drain region between each of a plurality of gates and isolation structures located on a semiconductor wafer. Also, the method includes implanting a dopant through openings formed in a channel stop mask and located between each of the plurality of gates and the isolation structures to form a channel stop between each of the source/drain regions and the isolation structures. Then, the method includes interconnecting each of the gates and source/drain regions to form an operative integrated circuit.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.